| NONSEC_WRITE | Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure. |
| RUN | Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 |
| CLEAR | Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time. |
| ALARM_ENAB | Enables the alarm. The alarm must be disabled while writing the alarm time. |
| PWRUP_ON_ALARM | Alarm wakes the chip from low power mode |
| ALARM | Alarm has fired. Write to 1 to clear the alarm. |
| USE_LPOSC | Switch to lposc as the source of the 1kHz timer tick |
| USE_XOSC | switch to xosc as the source of the 1kHz timer tick |
| USE_GPIO_1KHZ | switch to gpio as the source of the 1kHz timer tick |
| USE_GPIO_1HZ | Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference. |
| USING_XOSC | Timer is running from xosc |
| USING_LPOSC | Timer is running from lposc |
| USING_GPIO_1KHZ | Timer is running from a 1khz gpio source |
| USING_GPIO_1HZ | Timer is synchronised to a 1hz gpio source |